QR-Code Generator Based on FPGA

The IP-core for QR-code generation, which supports codes of the first version and the M-type level of correction (allows to recover information from damaged up to 15% code image) is developed. Based on this IP-core and the DE1SoC development board, containing the Cyclone V FPGA chip, the real QR-code generation device was implemented. The device uses the PS/2 interface to enter text data that should be encoded in the QR-code and output the result (generated code) on a VGA monitor as an image. The suggested device has the following structure: the control module, the IP-core for QR-code generation and I/O modules. The control module performs the general device management and implemented as the state machine, which has the following states: reset and memory cleaning, read the text that should be encoded from  the keyboard, create the main part of the QR-code, create correction data, combine the correction data with the main part of the QR-code, transform the result into a 21x21 pixel matrix and displaying the code on the screen. The input module reads the keyboard signals (synchronization and data signals) and converts them into the ASCII codes. To do this, on each falling edge of the synchronization signal the values of the data signal are registered and propagated to the 8-bit bus. Since the keyboard may have a contact bounce, this module additionally filters the received data using the delay filtering. The output module is the VGA controller that simply generates the necessary clock signals for the proper VGA monitor functioning. After the QR-code is generated, its matrix is enlarged and passed to the VGA controller. Also, in parallel with that, the text, which was encoded in the code, is printed on the display. The IP block for QR-code generation consists of three submodules. The first one receives a text in ASCII format (now only 14 characters are supported) and generates the primary sequence of data to be encrypted in the code. The second submodule calculates the correction data using the Reed-Solomon algorithm. To use this algorithm, the additional array is reserved to store the correction data. This array is filled with special information, depending on the level of correction and the code version number. The algorithm also requires tables of the forward and reverse Galois fields, which are precalculated and stored in the submodule’s ROM. The third module generates the matrix itself: it places the alignment patterns, the information of the used type of mask, level of correction, and adds timing patterns. After that, the mask superimposed on the data generated by the previous module, and the result is copied to the matrix code in the required order.